|
路线栈欢迎您!
您需要 登录 才可以下载或查看,没有帐号?立即注册
x
操作系统:Windows 10 x64
工具1:Allegro PCB Design XL (legacy) version 16.6-2015
工具2:PADS Layout VX.2.3
由PADS提供的参考手册,只要安装了PADS,就可以在X:\MentorGraphics\PADSVX.2.3\docs\pdfdocs里面找到该文件,文档原名《allegro2pads.pdf》。
情况1:Cadence、PADS安装在同一台机器上。
步骤1:
复制:<PADS安装目录>\SDD_HOME\translator\skill_scripts中的内容,以及<PADS安装目录>\SDD_HOME\translator\win32\bin\tech_translator.exe
到D:\Cadence\SPB_Data\pcbenv。
注意:Cadence一般是安装在C盘的,而我是将Cadence安装在D盘。
步骤2:
确保以下列出的三个环境变量已设置正确。
变量:SDD_HOME,值:D:\MentorGraphics\PADSVX.2.3\SDD_HOME(值取决于PADS的安装路径);
变量:AEX_BIN_ROOT,值:D:\Cadence\SPB_Data\pcbenv(值取决于Cadence的安装路径);
变量:AEX_ENABLE_JOBPREFS_LAYER_FIX,值:1。
步骤3:
创建一个新文件夹,将需要转换的.brd设计文件复制到这里面,使用Allegro PCB Design XL (legacy) 打开该设计文件。
在command提示窗口中输入下列命令:skill load "dfl_main.il",并按回车键。dfl_main.il文件来自<PADS安装目录>\SDD_HOME\translator\skill_scripts。
注意:第一次输入可能没有反应,你需要再次输入。反正我的就是这样,第一次输入之后,按回车键,只显示一个“t”。
根据Allegro to PADS? Layout Translator User's Guide(提取码:x8fs)给出的信息,执行脚本之后,如果有错误,是必须解决的,否则无法正确地生成输出文件。上面列出的信息,只有警告,我也不知道是否会产生什么特别严重的问题。
执行命令skill load "dfl_main.il"之后,还需要在Command提示窗口中输入另一命令main out,这会打开Allegro To Xpeditio...对话框,点击Start Translation启动转换,转换期间会弹出许多窗口,这个不用管。
注意:.brd设计文件的文件名不能带有空格或其它特殊字符,存放设计文件的文件夹也类似。我一开始转换的时候,就是因为文件名、文件夹名中带有空格,导致错误而折腾了很久。
转换完成之后,提示没有错误,但是有警告!始终不尽人意!
- Command > main out
- Please wait...extracting and processing technology file
- Starting Export techfile...
- techfile completed successfully, use Viewlog to review the log file.
- techfile completed successfully, use Viewlog to review the log file.
- Converting techfile...
- Executing command E:/Allegro2PADSLayout/GE300_LITE_PEDAL_DOWN_B02_MGC/Work\techconv.bat
- Techfile conversion successfull!
- extracting Layer Stackup
- extracting Design Rules
- Deleting Existing Classes File
- Deleting Existing Props File
- Deleting Existing Board Items File
- Exporting Electrical Constraints...
- Reading report definition file 'D:/Cadence/Cadence_SPB_16.6-2015/share/pcb/signal/reports.dat'.
- Finished reading report definition file successfully.
- Reading report definition file 'D:/Cadence/Cadence_SPB_16.6-2015/share/pcb/signal/custom_rep.dat'.
- Finished reading report definition file successfully.
- extracting device files
- extracting Net Properties
- extracting Board Extent
- Loading axlcore.cxt
- DCprocessWidthTable - DEFAULT width used
- extracting padstacks
- extracting padstack completed
- extracting Placement
- leaving placement
- extracting Device Pads
- devices pads extraction completed
- extracting Board Areas
- Loading skillExt.cxt
- Starting report...
- report completed successfully, use Viewlog to review the log file.
- report completed successfully, use Viewlog to review the log file.
- Exporting net information.
- There are 8 different component properties in this database.
- There are 103 different net properties in this database.
- Hierarchical net constraints have been flattened onto individual nets for export.
- There are no pin properties in this database.
- E:/Allegro2PADSLayout/GE300_LITE_PEDAL_DOWN_B02_MGC/Work/propdelay_raw.tmp has been created.
- Loading cmds.cxt
- E:/Allegro2PADSLayout/GE300_LITE_PEDAL_DOWN_B02_MGC/Work/LayoutDB.dfl Output Complete.
- Generating Padstack HKP FIle.
- ---------------------------
- Create .PAD Definitions.
- Create .HOLE Definitions.
- Create .PADSTACK Definitions.
- Generating Cell HKP File.
- ---------------------------
- Info: Database transaction started.
- Cell HKP Added temp instance of symbol: "CAP6D3"
- Cell HKP Added temp instance of symbol: "MARK_1MM"
- Cell HKP Added temp instance of symbol: "R0603"
- Cell HKP Added temp instance of symbol: "JL-0603RGB-TRB"
- Current Symbol: DRILL_HOLE_P_3MM2
- Current Symbol: R4D03
- Current Symbol: C0603
- Current Symbol: PH2MM54-12P_THRU90
- Current Symbol: JL-0603RGB-TRB
- Current Symbol: SW_12MMX12MM_SMD
- Current Symbol: TSSOP16
- Current Symbol: R0603
- Current Symbol: SOD-323
- Current Symbol: MARK_1MM
- Current Symbol: CAP6D3
- Removing temporarily added symbols.
- 4 symbols removed.
- Creating Net Properties
- Creating Net Class
- ---------------------- Al2Exp summary ----------------------
- Al2Exp - 0 error(s), 13 warning(s)
- Export log file saved at "E:/Allegro2PADSLayout/GE300_LITE_PEDAL_DOWN_B02_MGC\LogFiles\interfacelog.txt" file
- Run "show log" command to view log file
- ------------------------------ Done -------------------------------
复制代码
执行完上一步骤之后,在存放.brd设计文件的文件夹下面,会生成一些文件和文件夹。
先关闭Allegro PCB Design XL (legacy);打开PADS Layout,选菜单File > Import...
选择已执行过转换操作的设计文件;
正在执行转换...
完成转换之后生成的日志:
- Allegro(R) to PADS Layout Translator (Version VX.2.3) 05/22/19 09:41:27
- Copyright (c) 2018 Mentor Graphics Corp. - All rights reserved
- ------------------------------------------------------------
- Input folder: E:\Allegro2PADSLayout\GE300_LITE_PEDAL_DOWN_B02.brd
- Output folder: GE300_LITE_PEDAL_DOWN_B02_pads.pcb
- [I] Preparing data...
- Output file: GE300_LITE_PEDAL_DOWN_B02_pads.pcb
- [I] Loading...
- [I] Translating Xpedition design files from 'C:\Users\MK\AppData\Local\Temp\' to PADS Layout design file
- [I] Reading Pad Stacks...
- [I] Reading Cells...
- [I] Reading Part Numbers...
- [I] Reading Job Prefernces...
- [I] Reading Net Classes...
- [I] Reading Net Properties...
- [I] Reading Layout...
- [I] Translating data...
- [W] Discriminate Pad Entry rules found, and the rules were not translated.
- [W] Tie legs option was not found, and was translated to 2 spokes.
- [W] Hole name 'ROUND 0.4000 P' is duplicated. The hole was not translated.
- [W] Hole name 'ROUND 0.3000 P' is duplicated. The hole was not translated.
- [W] Hole name 'ROUND 1.0000 P' is duplicated. The hole was not translated.
- [W] Inner sizes of thermal pad 'AB00' will be changed, according to it's regular counterpart.
- [W] Part type name 'CAP POL1_CAP6D3__220UF/16V' contained invalid characters, and was translated to 'CAP_POL1_CAP6D3__220UF/16V'.
- [W] Part type name 'DRILL HOLE_DRILL_HOLE_P_3MM2_DR' contained invalid characters, and was translated to 'DRILL_HOLE_DRILL_HOLE_P_3MM2_DR'.
- [W] Part type name 'FERRITE BEAD_R0603_220R' contained invalid characters, and was translated to 'FERRITE_BEAD_R0603_220R'.
- [W] Part type name 'MARK POINT_MARK_1MM_MARK POINT' contained invalid characters, and was translated to 'MARK_POINT_MARK_1MM_MARK_POINT'.
- [W] Part type name 'RES PACK 2_R4D03_1K' contained invalid characters, and was translated to 'RES_PACK_2_R4D03_1K'.
- [W] Part type name 'RES PACK 2_R4D03_360R' contained invalid characters, and was translated to 'RES_PACK_2_R4D03_360R'.
- [W] Part type name 'RES PACK 2_R4D03_430R' contained invalid characters, and was translated to 'RES_PACK_2_R4D03_430R'.
- [W] Route outlines are not supported, and was not translated.
- [I] Completed
复制代码
完成导入后的PCB如下:
转换完后的文件乱糟糟,不能直接使用,处理方法请看Allegro PCB 转 PADS Layout 之后的修修补补。
|
|